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| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-27 13:56:16 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-27 13:56:16 -0800 |
| commit | cfb0366a18b0f3cab254636fdf534a3de76af8d5 (patch) | |
| tree | ef4aa0101b6082389a504ec1efd931705901e921 /techlibs/ice40 | |
| parent | ce6a690d27f3ce3b637f1d9be42b1efd744500d2 (diff) | |
| download | yosys-cfb0366a18b0f3cab254636fdf534a3de76af8d5.tar.gz yosys-cfb0366a18b0f3cab254636fdf534a3de76af8d5.tar.bz2 yosys-cfb0366a18b0f3cab254636fdf534a3de76af8d5.zip | |
Import tests from #1628
Diffstat (limited to 'techlibs/ice40')
| -rw-r--r-- | techlibs/ice40/ice40_opt.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/ice40/ice40_opt.cc b/techlibs/ice40/ice40_opt.cc index df10a2842..940a11063 100644 --- a/techlibs/ice40/ice40_opt.cc +++ b/techlibs/ice40/ice40_opt.cc @@ -139,8 +139,8 @@ static void run_ice40_opts(Module *module) log("Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) %s.%s: CO=%s\n", log_id(module), log_id(cell), log_signal(replacement_output)); cell->type = "$lut"; - auto I3 = cell->getPort(cell->getParam(ID(I3_IS_CI)).as_bool() ? ID(CI) : ID(I3)); - cell->setPort("\\A", { cell->getPort("\\I0"), inbit[0], inbit[1], I3 }); + auto I3 = get_bit_or_zero(cell->getPort(cell->getParam(ID(I3_IS_CI)).as_bool() ? ID(CI) : ID(I3))); + cell->setPort("\\A", { get_bit_or_zero(cell->getPort("\\I0")), inbit[0], inbit[1], I3 }); cell->setPort("\\Y", cell->getPort("\\O")); cell->unsetPort("\\B"); cell->unsetPort("\\CI"); |