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| author | Sergey <37293587+SergeyDegtyar@users.noreply.github.com> | 2019-08-29 21:07:34 +0300 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-08-29 21:07:34 +0300 |
| commit | d360693040dda29aba4ef2583e522c6ab88a4961 (patch) | |
| tree | 3de073925c8e3a4a613303ea807aeef12949a3d7 /techlibs/ice40 | |
| parent | d588c6898fb7cfebe52a71a48d6fb21d1623e61b (diff) | |
| parent | b8a9f73089234ed699a4057b50fd739a90abea43 (diff) | |
| download | yosys-d360693040dda29aba4ef2583e522c6ab88a4961.tar.gz yosys-d360693040dda29aba4ef2583e522c6ab88a4961.tar.bz2 yosys-d360693040dda29aba4ef2583e522c6ab88a4961.zip | |
Merge pull request #3 from YosysHQ/Sergey/tests_ice40
Merge my changes to tests_ice40 branch
Diffstat (limited to 'techlibs/ice40')
| -rw-r--r-- | techlibs/ice40/cells_sim.v | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v index 2205be27d..c7f3bdad2 100644 --- a/techlibs/ice40/cells_sim.v +++ b/techlibs/ice40/cells_sim.v @@ -141,8 +141,16 @@ module SB_CARRY (output CO, input I0, I1, CI); assign CO = (I0 && I1) || ((I0 || I1) && CI); endmodule -(* abc_box_id = 1, abc_carry="CI,CO", lib_whitebox *) -module \$__ICE40_FULL_ADDER (output CO, O, input A, B, CI); +(* abc_box_id = 1, lib_whitebox *) +module \$__ICE40_FULL_ADDER ( + (* abc_carry *) + output CO, + output O, + input A, + input B, + (* abc_carry *) + input CI +); SB_CARRY carry ( .I0(A), .I1(B), |