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| author | Eddie Hung <eddie@fpgeh.com> | 2019-04-21 15:19:02 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-21 15:19:02 -0700 |
| commit | d7f0700bae9785a55353ca76fe9f354ee4ffe03e (patch) | |
| tree | 7bcc7f07724ba68b863f02389e9972b74f3aed97 /techlibs/ice40 | |
| parent | 42a6e0b0b96208c5b0d79da5d8e31e9306a8aeae (diff) | |
| download | yosys-d7f0700bae9785a55353ca76fe9f354ee4ffe03e.tar.gz yosys-d7f0700bae9785a55353ca76fe9f354ee4ffe03e.tar.bz2 yosys-d7f0700bae9785a55353ca76fe9f354ee4ffe03e.zip | |
Convert to use #945
Diffstat (limited to 'techlibs/ice40')
| -rw-r--r-- | techlibs/ice40/cells_sim.v | 10 | ||||
| -rw-r--r-- | techlibs/ice40/synth_ice40.cc | 2 |
2 files changed, 3 insertions, 9 deletions
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v index a98bc30d9..93d970762 100644 --- a/techlibs/ice40/cells_sim.v +++ b/techlibs/ice40/cells_sim.v @@ -127,20 +127,14 @@ module SB_LUT4 (output O, input I0, I1, I2, I3); assign O = I0 ? s1[1] : s1[0]; endmodule -(* abc_box_id = 21 *) -`ifdef ABC_MODEL - (* whitebox *) -`endif +(* abc_box_id = 21, lib_whitebox *) module SB_CARRY (output CO, input I0, I1, CI); assign CO = (I0 && I1) || ((I0 || I1) && CI); endmodule // Positive Edge SiliconBlue FF Cells -(* abc_box_id = 1, abc_flop *) -`ifdef ABC_MODEL - (* whitebox *) -`endif +(* abc_box_id = 1, abc_flop, lib_whitebox *) module SB_DFF ((* abc_flop_q *) output `SB_DFF_REG, input C, (* abc_flop_d *) input D); `ifndef ABC_MODEL always @(posedge C) diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index 7cedecdff..718f9d9e0 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -240,7 +240,7 @@ struct SynthIce40Pass : public ScriptPass { if (check_label("begin")) { - run("read_verilog -wb -D ABC_MODEL +/ice40/cells_sim.v"); + run("read_verilog -lib -D ABC_MODEL +/ice40/cells_sim.v"); run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str())); run("proc"); } |