diff options
| author | Marcelina Kościelnicka <mwk@0x04.net> | 2020-08-20 21:59:37 +0200 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2020-08-21 01:46:06 +0200 |
| commit | 082cbcb4c7c4fa6984f86f8edb2e1d16e8ad3a41 (patch) | |
| tree | 8c901d28e7fbdb2ccbee2103543d2f5fd54c4703 /techlibs/intel/Makefile.inc | |
| parent | 034b9ec7161d67e861b1befcc4c550bff4481387 (diff) | |
| download | yosys-082cbcb4c7c4fa6984f86f8edb2e1d16e8ad3a41.tar.gz yosys-082cbcb4c7c4fa6984f86f8edb2e1d16e8ad3a41.tar.bz2 yosys-082cbcb4c7c4fa6984f86f8edb2e1d16e8ad3a41.zip | |
synth_intel: Remove incomplete Arria 10 GX support.
The techmap rules for this target do not work in the first place (note
lack of >2-input LUT mappings), and if proper support is ever added,
it'd be better placed in the synth_intel_alm backend.
Diffstat (limited to 'techlibs/intel/Makefile.inc')
| -rw-r--r-- | techlibs/intel/Makefile.inc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/intel/Makefile.inc b/techlibs/intel/Makefile.inc index 0c4899f06..b06cf5b72 100644 --- a/techlibs/intel/Makefile.inc +++ b/techlibs/intel/Makefile.inc @@ -8,7 +8,7 @@ $(eval $(call add_share_file,share/intel/common,techlibs/intel/common/brams_map_ $(eval $(call add_share_file,share/intel/common,techlibs/intel/common/ff_map.v)) # Add the cell models and mappings for the VQM backend -families := max10 arria10gx cyclone10lp cycloneiv cycloneive +families := max10 cyclone10lp cycloneiv cycloneive $(foreach family,$(families), $(eval $(call add_share_file,share/intel/$(family),techlibs/intel/$(family)/cells_sim.v))) $(foreach family,$(families), $(eval $(call add_share_file,share/intel/$(family),techlibs/intel/$(family)/cells_map.v))) #$(eval $(call add_share_file,share/intel/cycloneive,techlibs/intel/cycloneive/arith_map.v)) |