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| author | Dan Ravensloft <dan.ravensloft@gmail.com> | 2019-07-22 12:15:22 +0100 |
|---|---|---|
| committer | Dan Ravensloft <dan.ravensloft@gmail.com> | 2019-07-23 18:11:11 +0100 |
| commit | 67b4ce06e07fde80d5ac11cad4d673c501bdd421 (patch) | |
| tree | 26ba1373941ac0c83ff10a1edc530053ad1d4dec /techlibs/intel/common/brams.txt | |
| parent | c6d8692c9711e4b65aa89ad60986c9df7e053fc7 (diff) | |
| download | yosys-67b4ce06e07fde80d5ac11cad4d673c501bdd421.tar.gz yosys-67b4ce06e07fde80d5ac11cad4d673c501bdd421.tar.bz2 yosys-67b4ce06e07fde80d5ac11cad4d673c501bdd421.zip | |
intel: Map M9K BRAM only on families that have it
This regresses Cyclone V and Cyclone 10 substantially, but these
numbers were artificial, targeting a BRAM that they did not contain.
Amusingly, synth_intel still does better when synthesizing PicoSoC
than Quartus when neither are inferring block RAM.
Diffstat (limited to 'techlibs/intel/common/brams.txt')
| -rw-r--r-- | techlibs/intel/common/brams.txt | 33 |
1 files changed, 0 insertions, 33 deletions
diff --git a/techlibs/intel/common/brams.txt b/techlibs/intel/common/brams.txt deleted file mode 100644 index 3bf21afc9..000000000 --- a/techlibs/intel/common/brams.txt +++ /dev/null @@ -1,33 +0,0 @@ -bram $__M9K_ALTSYNCRAM_SINGLEPORT_FULL - init 1 - abits 13 @M1 - dbits 1 @M1 - abits 12 @M2 - dbits 2 @M2 - abits 11 @M3 - dbits 4 @M3 - abits 10 @M4 - dbits 8 @M4 - abits 10 @M5 - dbits 9 @M5 - abits 9 @M6 - dbits 16 @M6 - abits 9 @M7 - dbits 18 @M7 - abits 8 @M8 - dbits 32 @M8 - abits 8 @M9 - dbits 36 @M9 - groups 2 - ports 1 1 - wrmode 0 1 - enable 1 1 - transp 0 0 - clocks 2 3 - clkpol 2 3 -endbram - -match $__M9K_ALTSYNCRAM_SINGLEPORT_FULL - min efficiency 2 - make_transp -endmatch |