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| author | Miodrag Milanović <mmicko@gmail.com> | 2021-11-17 13:57:56 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-11-17 13:57:56 +0100 |
| commit | d0fda4c0ef1446f6d865b30d25a68e721834a4f2 (patch) | |
| tree | cfd193a711a070bb880535bfb8309489d64aca1d /techlibs/intel_alm/common/alm_sim.v | |
| parent | 07dde32bf1c507767d3dc3992f5248aa99b0d34d (diff) | |
| parent | c081c683a4672aa6b6b35d4cc8142719dacb882c (diff) | |
| download | yosys-d0fda4c0ef1446f6d865b30d25a68e721834a4f2.tar.gz yosys-d0fda4c0ef1446f6d865b30d25a68e721834a4f2.tar.bz2 yosys-d0fda4c0ef1446f6d865b30d25a68e721834a4f2.zip | |
Merge pull request #3080 from YosysHQ/micko/init_wire
Give initial wire unique ID, fixes #2914
Diffstat (limited to 'techlibs/intel_alm/common/alm_sim.v')
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