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| author | Dan Ravensloft <dan.ravensloft@gmail.com> | 2020-07-26 19:28:10 +0100 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2020-07-27 15:39:06 +0200 |
| commit | a2fb84fd0c5f57b601b6a3c4cee0b409d74b5d21 (patch) | |
| tree | 11c29855676708a2260ad9174514b2ed450b36cf /techlibs/intel_alm/common/quartus_rename.v | |
| parent | 62311b7ec0fc92fd78c38dd416551d460f1647a2 (diff) | |
| download | yosys-a2fb84fd0c5f57b601b6a3c4cee0b409d74b5d21.tar.gz yosys-a2fb84fd0c5f57b601b6a3c4cee0b409d74b5d21.tar.bz2 yosys-a2fb84fd0c5f57b601b6a3c4cee0b409d74b5d21.zip | |
intel_alm: direct M10K instantiation
This reverts commit a3a90f6377f251d3b6c5898eb1543f8832493bb8.
Diffstat (limited to 'techlibs/intel_alm/common/quartus_rename.v')
| -rw-r--r-- | techlibs/intel_alm/common/quartus_rename.v | 51 |
1 files changed, 50 insertions, 1 deletions
diff --git a/techlibs/intel_alm/common/quartus_rename.v b/techlibs/intel_alm/common/quartus_rename.v index 46ef2aa0d..9bc532ca2 100644 --- a/techlibs/intel_alm/common/quartus_rename.v +++ b/techlibs/intel_alm/common/quartus_rename.v @@ -88,6 +88,8 @@ endmodule module MISTRAL_MLAB(input [4:0] A1ADDR, input A1DATA, A1EN, CLK1, input [4:0] B1ADDR, output B1DATA); +parameter _TECHMAP_CELLNAME_ = ""; + // Here we get to an unfortunate situation. The cell has a mem_init0 parameter, // which takes in a hexadecimal string that could be used to initialise RAM. // In the vendor simulation models, this appears to work fine, but Quartus, @@ -99,7 +101,7 @@ module MISTRAL_MLAB(input [4:0] A1ADDR, input A1DATA, A1EN, CLK1, input [4:0] B1 // or an undocumented way to get Quartus to initialise from mem_init0 is found. `MLAB #( - .logical_ram_name("MISTRAL_MLAB"), + .logical_ram_name(_TECHMAP_CELLNAME_), .logical_ram_depth(32), .logical_ram_width(1), .mixed_port_feed_through_mode("Dont Care"), @@ -123,6 +125,53 @@ module MISTRAL_MLAB(input [4:0] A1ADDR, input A1DATA, A1EN, CLK1, input [4:0] B1 endmodule +module MISTRAL_M10K(A1ADDR, A1DATA, A1EN, CLK1, B1ADDR, B1DATA, B1EN); + +parameter CFG_ABITS = 10; +parameter CFG_DBITS = 10; + +parameter _TECHMAP_CELLNAME_ = ""; + +input [CFG_ABITS-1:0] A1ADDR, B1ADDR; +input [CFG_DBITS-1:0] A1DATA; +input CLK1, A1EN, B1EN; +output [CFG_DBITS-1:0] B1DATA; + +// Much like the MLAB, the M10K has mem_init[01234] parameters which would let +// you initialise the RAM cell via hex literals. If they were implemented. + +cyclonev_ram_block #( + .operation_mode("dual_port"), + .logical_ram_name(_TECHMAP_CELLNAME_), + .port_a_address_width(CFG_ABITS), + .port_a_data_width(CFG_DBITS), + .port_a_logical_ram_depth(2**CFG_ABITS), + .port_a_logical_ram_width(CFG_DBITS), + .port_a_first_address(0), + .port_a_last_address(2**CFG_ABITS - 1), + .port_a_first_bit_number(0), + .port_b_address_width(CFG_ABITS), + .port_b_data_width(CFG_DBITS), + .port_b_logical_ram_depth(2**CFG_ABITS), + .port_b_logical_ram_width(CFG_DBITS), + .port_b_first_address(0), + .port_b_last_address(2**CFG_ABITS - 1), + .port_b_first_bit_number(0), + .port_b_address_clock("clock0"), + .port_b_read_enable_clock("clock0") +) _TECHMAP_REPLACE_ ( + .portaaddr(A1ADDR), + .portadatain(A1DATA), + .portawe(A1EN), + .portbaddr(B1ADDR), + .portbdataout(B1DATA), + .portbre(B1EN), + .clk0(CLK1) +); + +endmodule + + module MISTRAL_MUL27X27(input [26:0] A, B, output [53:0] Y); `MAC #(.ax_width(27), .ay_scan_in_width(27), .result_a_width(54), .operation_mode("M27x27")) _TECHMAP_REPLACE_ (.ax(A), .ay(B), .resulta(Y)); |