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| author | Lofty <dan.ravensloft@gmail.com> | 2021-11-24 21:20:40 +0000 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2021-11-25 17:20:36 +0100 |
| commit | a31c8a82be4ec98dbe58ce7efdde3a372b9767e0 (patch) | |
| tree | fb291eb084201f1f1669e36cb6533b9adb43d101 /techlibs/intel_alm/common/quartus_rename.v | |
| parent | 77327b2544a30b15e8efc79e1f62661ff25d306c (diff) | |
| download | yosys-a31c8a82be4ec98dbe58ce7efdde3a372b9767e0.tar.gz yosys-a31c8a82be4ec98dbe58ce7efdde3a372b9767e0.tar.bz2 yosys-a31c8a82be4ec98dbe58ce7efdde3a372b9767e0.zip | |
intel_alm: preliminary Arria V support
Diffstat (limited to 'techlibs/intel_alm/common/quartus_rename.v')
| -rw-r--r-- | techlibs/intel_alm/common/quartus_rename.v | 13 |
1 files changed, 12 insertions, 1 deletions
diff --git a/techlibs/intel_alm/common/quartus_rename.v b/techlibs/intel_alm/common/quartus_rename.v index 57321de77..5850f6907 100644 --- a/techlibs/intel_alm/common/quartus_rename.v +++ b/techlibs/intel_alm/common/quartus_rename.v @@ -2,14 +2,25 @@ `define LCELL cyclonev_lcell_comb `define MAC cyclonev_mac `define MLAB cyclonev_mlab_cell +`define RAM_BLOCK cyclonev_ram_block `define IBUF cyclonev_io_ibuf `define OBUF cyclonev_io_obuf `define CLKENA cyclonev_clkena `endif +`ifdef arriav +`define LCELL arriav_lcell_comb +`define MAC arriav_mac +`define MLAB arriav_mlab_cell +`define RAM_BLOCK arriav_ram_block +`define IBUF arriav_io_ibuf +`define OBUF arriav_io_obuf +`define CLKENA arriav_clkena +`endif `ifdef cyclone10gx `define LCELL cyclone10gx_lcell_comb `define MAC cyclone10gx_mac `define MLAB cyclone10gx_mlab_cell +`define RAM_BLOCK cyclone10gx_ram_block `define IBUF cyclone10gx_io_ibuf `define OBUF cyclone10gx_io_obuf `define CLKENA cyclone10gx_clkena @@ -146,7 +157,7 @@ output [CFG_DBITS-1:0] B1DATA; // Much like the MLAB, the M10K has mem_init[01234] parameters which would let // you initialise the RAM cell via hex literals. If they were implemented. -cyclonev_ram_block #( +`RAM_BLOCK #( .operation_mode("dual_port"), .logical_ram_name(_TECHMAP_CELLNAME_), .port_a_address_width(CFG_ABITS), |