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| author | gatecat <gatecat@ds0.me> | 2021-05-15 14:34:48 +0100 |
|---|---|---|
| committer | gatecat <gatecat@ds0.me> | 2021-05-15 22:37:06 +0100 |
| commit | eb106732d94322fb5b48fbff0420ce5a6fc83eb9 (patch) | |
| tree | 3ed44e78ce74793b5d5625c04475641e6e977a33 /techlibs/intel_alm/common/quartus_rename.v | |
| parent | 5dba138c87762d4b5bb7b9348da372a92fab1cc0 (diff) | |
| download | yosys-eb106732d94322fb5b48fbff0420ce5a6fc83eb9.tar.gz yosys-eb106732d94322fb5b48fbff0420ce5a6fc83eb9.tar.bz2 yosys-eb106732d94322fb5b48fbff0420ce5a6fc83eb9.zip | |
intel_alm: Add global buffer insertion
Signed-off-by: gatecat <gatecat@ds0.me>
Diffstat (limited to 'techlibs/intel_alm/common/quartus_rename.v')
| -rw-r--r-- | techlibs/intel_alm/common/quartus_rename.v | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/techlibs/intel_alm/common/quartus_rename.v b/techlibs/intel_alm/common/quartus_rename.v index 964a094dd..57321de77 100644 --- a/techlibs/intel_alm/common/quartus_rename.v +++ b/techlibs/intel_alm/common/quartus_rename.v @@ -4,6 +4,7 @@ `define MLAB cyclonev_mlab_cell `define IBUF cyclonev_io_ibuf `define OBUF cyclonev_io_obuf +`define CLKENA cyclonev_clkena `endif `ifdef cyclone10gx `define LCELL cyclone10gx_lcell_comb @@ -11,6 +12,7 @@ `define MLAB cyclone10gx_mlab_cell `define IBUF cyclone10gx_io_ibuf `define OBUF cyclone10gx_io_obuf +`define CLKENA cyclone10gx_clkena `endif module __MISTRAL_VCC(output Q); @@ -277,3 +279,17 @@ module MISTRAL_IO(output PAD, input I, OE, output O); .oe(OE) ); endmodule + +module MISTRAL_CLKBUF (input A, output Q); +`CLKENA #( + .clock_type("auto"), + .ena_register_mode("always enabled"), + .ena_register_power_up("high"), + .disable_mode("low"), + .test_syn("high") +) _TECHMAP_REPLACE_ ( + .inclk(A), + .ena(1'b1), + .outclk(Q) +); +endmodule |