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| author | William D. Jones <thor0505@comcast.net> | 2020-11-17 12:49:15 -0500 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2021-02-23 17:39:58 +0100 |
| commit | b87f6a09069eb2b1dce3ff197691e5f2e76dff38 (patch) | |
| tree | cfc07ce0108da0bc0dd8b0ab1477c91aa9064f2a /techlibs/machxo2/cells_sim.v | |
| parent | 88c8f812602c25ef0a062002bede8fe737b6ac77 (diff) | |
| download | yosys-b87f6a09069eb2b1dce3ff197691e5f2e76dff38.tar.gz yosys-b87f6a09069eb2b1dce3ff197691e5f2e76dff38.tar.bz2 yosys-b87f6a09069eb2b1dce3ff197691e5f2e76dff38.zip | |
machxo2: Fix typos. test/arch/run-test.sh passes.
Diffstat (limited to 'techlibs/machxo2/cells_sim.v')
| -rw-r--r-- | techlibs/machxo2/cells_sim.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/machxo2/cells_sim.v b/techlibs/machxo2/cells_sim.v index 06fbe2023..22b4fcf3c 100644 --- a/techlibs/machxo2/cells_sim.v +++ b/techlibs/machxo2/cells_sim.v @@ -26,7 +26,7 @@ module FACADE_FF #( parameter SRMODE = "LSR_OVER_CE", parameter REGSET = "SET" ) ( - input CLK, D, LSR, CE, + input CLK, DI, LSR, CE, output reg Q ); |