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module LUT4 #(
parameter [15:0] INIT = 0
) (
input A, B, C, D,
output F
);
wire [3:0] I;
wire [3:0] I_pd;
genvar ii;
generate
for (ii = 0; ii < 4; ii = ii + 1'b1)
assign I_pd[ii] = (I[ii] === 1'bz) ? 1'b0 : I[ii];
endgenerate
assign I = {D, C, B, A};
assign F = INIT[I_pd];
endmodule
module FACADE_FF #(
parameter GSR = "ENABLED",
parameter CEMUX = "1",
parameter CLKMUX = "0",
parameter LSRMUX = "LSR",
parameter LSRONMUX = "LSRMUX",
parameter SRMODE = "LSR_OVER_CE",
parameter REGSET = "SET"
) (
input CLK, DI, LSR, CE,
output reg Q
);
wire muxce;
generate
case (CEMUX)
"1": assign muxce = 1'b1;
"0": assign muxce = 1'b0;
"INV": assign muxce = ~CE;
default: assign muxce = CE;
endcase
endgenerate
wire muxlsr = (LSRMUX == "INV") ? ~LSR : LSR;
wire muxclk = (CLKMUX == "INV") ? ~CLK : CLK;
assign srval = (REGSET == "SET") ? 1'b1 : 1'b0;
generate
if (SRMODE == "ASYNC") begin
always @(posedge muxclk, posedge muxlsr)
if (muxlsr)
Q <= srval;
else if (muxce)
Q <= DI;
end else begin
always @(posedge muxclk)
if (muxlsr)
Q <= srval;
else if (muxce)
Q <= DI;
end
endgenerate
endmodule
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