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| author | Lofty <dan.ravensloft@gmail.com> | 2021-04-12 10:33:40 +0100 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2021-04-17 20:54:58 +0200 |
| commit | dce037a62c5bda9a8256d271d39b06be366120e8 (patch) | |
| tree | 67d022cbceb487f5359215d7c9ca51959100f549 /techlibs/quicklogic/pp3_cells_sim.v | |
| parent | a58571d0fe8971cb7d3a619a31b2c21be6d75bac (diff) | |
| download | yosys-dce037a62c5bda9a8256d271d39b06be366120e8.tar.gz yosys-dce037a62c5bda9a8256d271d39b06be366120e8.tar.bz2 yosys-dce037a62c5bda9a8256d271d39b06be366120e8.zip | |
quicklogic: ABC9 synthesis
Diffstat (limited to 'techlibs/quicklogic/pp3_cells_sim.v')
| -rw-r--r-- | techlibs/quicklogic/pp3_cells_sim.v | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/techlibs/quicklogic/pp3_cells_sim.v b/techlibs/quicklogic/pp3_cells_sim.v index 61d1ee314..5820d7a9e 100644 --- a/techlibs/quicklogic/pp3_cells_sim.v +++ b/techlibs/quicklogic/pp3_cells_sim.v @@ -147,11 +147,10 @@ module dffepc ( ); parameter [0:0] INIT = 1'b0; - // The CLR => Q and PRE => Q paths are commented out due to YosysHQ/yosys#2530. specify if (EN) (posedge CLK => (Q : D)) = 1701; // QCK -> QZ - // if (CLR) (CLR => Q) = 967; // QRT -> QZ - // if (PRE) (PRE => Q) = 1252; // QST -> QZ + if (CLR) (CLR => Q) = 967; // QRT -> QZ + if (PRE) (PRE => Q) = 1252; // QST -> QZ $setup(D, posedge CLK, 216); // QCK -> QDS $setup(EN, posedge CLK, 590); // QCK -> QEN endspecify |