diff options
Diffstat (limited to 'techlibs/quicklogic/pp3_cells_sim.v')
| -rw-r--r-- | techlibs/quicklogic/pp3_cells_sim.v | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/techlibs/quicklogic/pp3_cells_sim.v b/techlibs/quicklogic/pp3_cells_sim.v index 61d1ee314..5820d7a9e 100644 --- a/techlibs/quicklogic/pp3_cells_sim.v +++ b/techlibs/quicklogic/pp3_cells_sim.v @@ -147,11 +147,10 @@ module dffepc ( ); parameter [0:0] INIT = 1'b0; - // The CLR => Q and PRE => Q paths are commented out due to YosysHQ/yosys#2530. specify if (EN) (posedge CLK => (Q : D)) = 1701; // QCK -> QZ - // if (CLR) (CLR => Q) = 967; // QRT -> QZ - // if (PRE) (PRE => Q) = 1252; // QST -> QZ + if (CLR) (CLR => Q) = 967; // QRT -> QZ + if (PRE) (PRE => Q) = 1252; // QST -> QZ $setup(D, posedge CLK, 216); // QCK -> QDS $setup(EN, posedge CLK, 590); // QCK -> QEN endspecify |