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| author | Eddie Hung <eddie@fpgeh.com> | 2019-11-21 16:32:52 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-11-21 16:32:52 -0800 |
| commit | fe3627523437cfddc069ec9e2c4607a1aaf9ce2e (patch) | |
| tree | adb60aab9fa9641ad58fef2da02f34fb21367d93 /techlibs/xilinx/abc9_map.v | |
| parent | 39fdcb892b1b65363fdf7c1bc6d9e2612c1c38e6 (diff) | |
| parent | a5767474830756319ce0fff53b81573701ec0cd2 (diff) | |
| download | yosys-fe3627523437cfddc069ec9e2c4607a1aaf9ce2e.tar.gz yosys-fe3627523437cfddc069ec9e2c4607a1aaf9ce2e.tar.bz2 yosys-fe3627523437cfddc069ec9e2c4607a1aaf9ce2e.zip | |
Merge remote-tracking branch 'origin/xaig_dff' into eddie/xaig_dff_adff
Diffstat (limited to 'techlibs/xilinx/abc9_map.v')
| -rw-r--r-- | techlibs/xilinx/abc9_map.v | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/techlibs/xilinx/abc9_map.v b/techlibs/xilinx/abc9_map.v index fc224e832..9913b229f 100644 --- a/techlibs/xilinx/abc9_map.v +++ b/techlibs/xilinx/abc9_map.v @@ -96,7 +96,7 @@ module FDRE_1 (output reg Q, input C, CE, D, R); parameter [0:0] INIT = 1'b0; wire $nextQ; FDRE_1 #( - .INIT(|0), + .INIT(INIT), ) _TECHMAP_REPLACE_ ( .D(D), .Q($nextQ), .C(C), .CE(CE), .R(R) ); @@ -209,7 +209,7 @@ module FDPE_1 (output reg Q, input C, CE, D, PRE); endmodule module FDSE (output reg Q, input C, CE, D, S); - parameter [0:0] INIT = 1'b0; + parameter [0:0] INIT = 1'b1; parameter [0:0] IS_C_INVERTED = 1'b0; parameter [0:0] IS_D_INVERTED = 1'b0; parameter [0:0] IS_S_INVERTED = 1'b0; @@ -230,10 +230,10 @@ module FDSE (output reg Q, input C, CE, D, S); wire _TECHMAP_REPLACE_.$abc9_currQ = Q; endmodule module FDSE_1 (output reg Q, input C, CE, D, S); - parameter [0:0] INIT = 1'b0; + parameter [0:0] INIT = 1'b1; wire $nextQ; FDSE_1 #( - .INIT(|0), + .INIT(INIT), ) _TECHMAP_REPLACE_ ( .D(D), .Q($nextQ), .C(C), .CE(CE), .S(S) ); |