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| author | Eddie Hung <eddie@fpgeh.com> | 2020-03-04 13:37:09 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-03-04 13:37:09 -0800 |
| commit | 6eb528277e73a978ace7d6f693215d9ff92f898d (patch) | |
| tree | f4e882e5504bda5674266fe54a37daab15b92519 /techlibs/xilinx/abc9_unmap.v | |
| parent | 0ec971444b0ae226417ac36d408569374269e799 (diff) | |
| parent | 7b543fdb0cbd45dcf2d3322518cc02a01cc1e43f (diff) | |
| download | yosys-6eb528277e73a978ace7d6f693215d9ff92f898d.tar.gz yosys-6eb528277e73a978ace7d6f693215d9ff92f898d.tar.bz2 yosys-6eb528277e73a978ace7d6f693215d9ff92f898d.zip | |
Merge pull request #1735 from YosysHQ/eddie/abc9_dsp48e1
xilinx: cleanup DSP48E1 handling for abc9
Diffstat (limited to 'techlibs/xilinx/abc9_unmap.v')
| -rw-r--r-- | techlibs/xilinx/abc9_unmap.v | 13 |
1 files changed, 11 insertions, 2 deletions
diff --git a/techlibs/xilinx/abc9_unmap.v b/techlibs/xilinx/abc9_unmap.v index c02cc196a..5604ceb0a 100644 --- a/techlibs/xilinx/abc9_unmap.v +++ b/techlibs/xilinx/abc9_unmap.v @@ -36,8 +36,7 @@ module $__ABC9_RAM7(input A, input [6:0] S, output Y); assign Y = A; endmodule -(* techmap_celltype = "$__ABC9_DSP48E1_MULT $__ABC9_DSP48E1_MULT_DPORT $__ABC9_DSP48E1" *) -module $ABC9_DSP48E1( +module $__ABC9_DSP48E1( input [29:0] $A, input [17:0] $B, input [47:0] $C, @@ -48,5 +47,15 @@ module $ABC9_DSP48E1( output [47:0] P, output [47:0] PCOUT ); + parameter integer ADREG = 1; + parameter integer AREG = 1; + parameter integer BREG = 1; + parameter integer CREG = 1; + parameter integer DREG = 1; + parameter integer MREG = 1; + parameter integer PREG = 1; + parameter USE_DPORT = "FALSE"; + parameter USE_MULT = "MULTIPLY"; + assign P = $P, PCOUT = $PCOUT; endmodule |