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| author | Eddie Hung <eddie@fpgeh.com> | 2020-03-04 12:04:02 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-03-04 12:04:02 -0800 |
| commit | 7b543fdb0cbd45dcf2d3322518cc02a01cc1e43f (patch) | |
| tree | ab1520d1aa2b19eb44cb46611b425431567ca0b0 /techlibs/xilinx/abc9_unmap.v | |
| parent | 512596760b947a9ac9088856490970d0930dd951 (diff) | |
| download | yosys-7b543fdb0cbd45dcf2d3322518cc02a01cc1e43f.tar.gz yosys-7b543fdb0cbd45dcf2d3322518cc02a01cc1e43f.tar.bz2 yosys-7b543fdb0cbd45dcf2d3322518cc02a01cc1e43f.zip | |
xilinx: consider DSP48E1.ADREG
Diffstat (limited to 'techlibs/xilinx/abc9_unmap.v')
| -rw-r--r-- | techlibs/xilinx/abc9_unmap.v | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/techlibs/xilinx/abc9_unmap.v b/techlibs/xilinx/abc9_unmap.v index b8d0c4dc0..5604ceb0a 100644 --- a/techlibs/xilinx/abc9_unmap.v +++ b/techlibs/xilinx/abc9_unmap.v @@ -47,6 +47,7 @@ module $__ABC9_DSP48E1( output [47:0] P, output [47:0] PCOUT ); + parameter integer ADREG = 1; parameter integer AREG = 1; parameter integer BREG = 1; parameter integer CREG = 1; |