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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-13 11:45:55 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-13 11:45:55 -0700 |
| commit | 247a63f55df2e85f0aa15a9a05f436c1225f9ec1 (patch) | |
| tree | 8a6000efa5cf861a144997aca82025675542d1e4 /techlibs/xilinx/abc_unmap.v | |
| parent | e235dd07854ad31617a4609c59dbdeacb9323ad0 (diff) | |
| download | yosys-247a63f55df2e85f0aa15a9a05f436c1225f9ec1.tar.gz yosys-247a63f55df2e85f0aa15a9a05f436c1225f9ec1.tar.bz2 yosys-247a63f55df2e85f0aa15a9a05f436c1225f9ec1.zip | |
Add support for MULT and DPORT
Diffstat (limited to 'techlibs/xilinx/abc_unmap.v')
| -rw-r--r-- | techlibs/xilinx/abc_unmap.v | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/techlibs/xilinx/abc_unmap.v b/techlibs/xilinx/abc_unmap.v index bcb1069bc..f9b5bd518 100644 --- a/techlibs/xilinx/abc_unmap.v +++ b/techlibs/xilinx/abc_unmap.v @@ -30,14 +30,13 @@ endmodule module \$__ABC_DSP48E1_REG (input [47:0] I, output [47:0] O, output Q); assign O = I; endmodule -module \$__ABC_DSP48E1_MULT_P_MUX (input Aq, Bq, Cq, Dq, ADq, Mq, input [47:0] P, input Pq, output [47:0] O); - assign O = P; -endmodule -module \$__ABC_DSP48E1_MULT_PCOUT_MUX (input Aq, Bq, Cq, Dq, ADq, Mq, input [47:0] P, input Pq, output [47:0] O); +(* techmap_celltype = "$__ABC_DSP48E1_MULT_P_MUX $__ABC_DSP48E1_MULT_PCOUT_MUX $__ABC_DSP48E1_MULT_DPORT_P_MUX $__ABC_DSP48E1_MULT_DPORT_PCOUT_MUX" *) +module \$__ABC_DSP48E1_MUX (input Aq, Bq, Cq, Dq, ADq, Mq, input [47:0] P, input Pq, output [47:0] O); assign O = P; endmodule -module \$__ABC_DSP48E1_MULT ( +(* techmap_celltype = "$__ABC_DSP48E1_MULT $__ABC_DSP48E1_MULT_DPORT" *) +module \$__ABC_DSP48E1 ( output [29:0] ACOUT, output [17:0] BCOUT, output reg CARRYCASCOUT, |