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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-13 12:05:14 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-13 12:05:14 -0700 |
| commit | d0b202c58d45145e79243caac55f155328008d39 (patch) | |
| tree | 31d20d6b11b116a8c8b5d5928dd047e2da6a924a /techlibs/xilinx/abc_unmap.v | |
| parent | 247a63f55df2e85f0aa15a9a05f436c1225f9ec1 (diff) | |
| download | yosys-d0b202c58d45145e79243caac55f155328008d39.tar.gz yosys-d0b202c58d45145e79243caac55f155328008d39.tar.bz2 yosys-d0b202c58d45145e79243caac55f155328008d39.zip | |
Add no MULT no DPORT config
Diffstat (limited to 'techlibs/xilinx/abc_unmap.v')
| -rw-r--r-- | techlibs/xilinx/abc_unmap.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/xilinx/abc_unmap.v b/techlibs/xilinx/abc_unmap.v index f9b5bd518..2ef507bf2 100644 --- a/techlibs/xilinx/abc_unmap.v +++ b/techlibs/xilinx/abc_unmap.v @@ -30,12 +30,12 @@ endmodule module \$__ABC_DSP48E1_REG (input [47:0] I, output [47:0] O, output Q); assign O = I; endmodule -(* techmap_celltype = "$__ABC_DSP48E1_MULT_P_MUX $__ABC_DSP48E1_MULT_PCOUT_MUX $__ABC_DSP48E1_MULT_DPORT_P_MUX $__ABC_DSP48E1_MULT_DPORT_PCOUT_MUX" *) +(* techmap_celltype = "$__ABC_DSP48E1_MULT_P_MUX $__ABC_DSP48E1_MULT_PCOUT_MUX $__ABC_DSP48E1_MULT_DPORT_P_MUX $__ABC_DSP48E1_MULT_DPORT_PCOUT_MUX $__ABC_DSP48E1_P_MUX $__ABC_DSP48E1_PCOUT_MUX" *) module \$__ABC_DSP48E1_MUX (input Aq, Bq, Cq, Dq, ADq, Mq, input [47:0] P, input Pq, output [47:0] O); assign O = P; endmodule -(* techmap_celltype = "$__ABC_DSP48E1_MULT $__ABC_DSP48E1_MULT_DPORT" *) +(* techmap_celltype = "$__ABC_DSP48E1_MULT $__ABC_DSP48E1_MULT_DPORT $__ABC_DSP48E1" *) module \$__ABC_DSP48E1 ( output [29:0] ACOUT, output [17:0] BCOUT, |