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author | Eddie Hung <eddie@fpgeh.com> | 2019-07-10 16:12:33 -0700 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-10 16:12:33 -0700 |
commit | 73c8f1a59e69c5c2f06827d365afc6504fdfad82 (patch) | |
tree | e0a084bb8b37f6f519db565a81241ad96a1dea54 /techlibs/xilinx/abc_xc7.box | |
parent | 052060f10906ca859d2313b86800e110bd34b79f (diff) | |
download | yosys-73c8f1a59e69c5c2f06827d365afc6504fdfad82.tar.gz yosys-73c8f1a59e69c5c2f06827d365afc6504fdfad82.tar.bz2 yosys-73c8f1a59e69c5c2f06827d365afc6504fdfad82.zip |
Fix box numbering
Diffstat (limited to 'techlibs/xilinx/abc_xc7.box')
-rw-r--r-- | techlibs/xilinx/abc_xc7.box | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/techlibs/xilinx/abc_xc7.box b/techlibs/xilinx/abc_xc7.box index 69ff9aeab..1e1afbc1d 100644 --- a/techlibs/xilinx/abc_xc7.box +++ b/techlibs/xilinx/abc_xc7.box @@ -59,20 +59,20 @@ RAM128X1D 7 0 17 2 # Inputs: C CE D R \$pastQ # Outputs: Q -FDRE 7 1 5 1 +FDRE 8 1 5 1 - 109 -46 358 0 # Inputs: C CE D S \$pastQ # Outputs: Q -FDSE 8 0 5 1 +FDSE 9 0 5 1 - 109 -46 358 0 # Inputs: C CE CLR D \$pastQ # Outputs: Q -FDCE 9 0 5 1 +FDCE 10 0 5 1 - 109 - -46 0 # Inputs: C CE D PRE \$pastQ # Outputs: Q -FDPE 10 0 5 1 +FDPE 11 0 5 1 - 109 -46 - 0 |