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| author | Clifford Wolf <clifford@clifford.at> | 2015-01-06 13:33:51 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-01-06 13:33:51 +0100 |
| commit | 9c7f47bbd5fc190578054a6d018760c2f2b62c03 (patch) | |
| tree | 2349200118a55b18778b04aa858e9a2e33397767 /techlibs/xilinx/brams.v | |
| parent | 462b22f44fae71767991bd4eb502d009149b3995 (diff) | |
| download | yosys-9c7f47bbd5fc190578054a6d018760c2f2b62c03.tar.gz yosys-9c7f47bbd5fc190578054a6d018760c2f2b62c03.tar.bz2 yosys-9c7f47bbd5fc190578054a6d018760c2f2b62c03.zip | |
Towards Xilinx bram support
Diffstat (limited to 'techlibs/xilinx/brams.v')
| -rw-r--r-- | techlibs/xilinx/brams.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/xilinx/brams.v b/techlibs/xilinx/brams.v index aaab8d475..49219c8a1 100644 --- a/techlibs/xilinx/brams.v +++ b/techlibs/xilinx/brams.v @@ -13,8 +13,8 @@ module \$__XILINX_RAMB36_SDP72 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN input [71:0] B1DATA; input [7:0] B1EN; - wire [15:0] A1ADDR_16 = A1ADDR; - wire [15:0] B1ADDR_16 = B1ADDR; + wire [15:0] A1ADDR_16 = {A1ADDR, 6'b0}; + wire [15:0] B1ADDR_16 = {B1ADDR, 6'b0}; wire [7:0] DIP, DOP; wire [63:0] DI, DO; |