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| author | Marcin Kościelnicki <marcin@symbioticeda.com> | 2019-11-18 03:47:56 +0100 |
|---|---|---|
| committer | Marcin Kościelnicki <mwk@0x04.net> | 2019-11-19 01:00:58 +0100 |
| commit | 7a9081440c33af05cd5b24b4eb8907ac2ba4876a (patch) | |
| tree | c4b9467b060b3f7c5b00d36e60db0b69855ec1c8 /techlibs/xilinx/cells_xtra.py | |
| parent | 9ee3c57e460b15acb8e1503e97fc35aa6eed0661 (diff) | |
| download | yosys-7a9081440c33af05cd5b24b4eb8907ac2ba4876a.tar.gz yosys-7a9081440c33af05cd5b24b4eb8907ac2ba4876a.tar.bz2 yosys-7a9081440c33af05cd5b24b4eb8907ac2ba4876a.zip | |
xilinx: Add simulation models for MULT18X18* and DSP48A*.
This adds simulation models for the following primitives:
- MULT18X18 and MULT18X18S (Virtex 2*, Spartan 3)
- MULT18X18SIO (Spartan 3E, Spartan 3A)
- DSP48A (Spartan 3A DSP) — implemented in terms of DSP48A1
- DSP48A1 (Spartan 6)
Diffstat (limited to 'techlibs/xilinx/cells_xtra.py')
| -rw-r--r-- | techlibs/xilinx/cells_xtra.py | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/techlibs/xilinx/cells_xtra.py b/techlibs/xilinx/cells_xtra.py index ef7ce856a..f401ebe78 100644 --- a/techlibs/xilinx/cells_xtra.py +++ b/techlibs/xilinx/cells_xtra.py @@ -204,11 +204,11 @@ CELLS = [ Cell('URAM288_BASE', port_attrs={'CLK': ['clkbuf_sink']}), # Multipliers and DSP. - Cell('MULT18X18'), # Spartan 3 - Cell('MULT18X18S', port_attrs={'C': ['clkbuf_sink']}), # Spartan 3 - Cell('MULT18X18SIO', port_attrs={'CLK': ['clkbuf_sink']}), # Spartan 3E - Cell('DSP48A', port_attrs={'CLK': ['clkbuf_sink']}), # Spartan 3A DSP - Cell('DSP48A1', port_attrs={'CLK': ['clkbuf_sink']}), # Spartan 6 + # Cell('MULT18X18'), # Virtex 2, Spartan 3 + # Cell('MULT18X18S', port_attrs={'C': ['clkbuf_sink']}), # Spartan 3 + # Cell('MULT18X18SIO', port_attrs={'CLK': ['clkbuf_sink']}), # Spartan 3E + # Cell('DSP48A', port_attrs={'CLK': ['clkbuf_sink']}), # Spartan 3A DSP + # Cell('DSP48A1', port_attrs={'CLK': ['clkbuf_sink']}), # Spartan 6 Cell('DSP48', port_attrs={'CLK': ['clkbuf_sink']}), # Virtex 4 Cell('DSP48E', port_attrs={'CLK': ['clkbuf_sink']}), # Virtex 5 #Cell('DSP48E1', port_attrs={'CLK': ['clkbuf_sink']}), # Virtex 6 / Series 7 |