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| author | Eddie Hung <eddie@fpgeh.com> | 2019-11-27 00:48:22 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-11-27 00:48:22 -0800 |
| commit | 8c813632b6c1557f5123ea0cece2738fad40b89b (patch) | |
| tree | 629e014e6e5fa25c1615b36876110acfbe42d48c /techlibs/xilinx/cells_xtra.py | |
| parent | 969f51141535ac70d8fbb2a0e2da7ee2aba833b8 (diff) | |
| download | yosys-8c813632b6c1557f5123ea0cece2738fad40b89b.tar.gz yosys-8c813632b6c1557f5123ea0cece2738fad40b89b.tar.bz2 yosys-8c813632b6c1557f5123ea0cece2738fad40b89b.zip | |
Revert "submod to bitty rather bussy, for bussy wires used as input and output"
This reverts commit cba3073026711e7683c46ba091c56a5c5a041a45.
Diffstat (limited to 'techlibs/xilinx/cells_xtra.py')
0 files changed, 0 insertions, 0 deletions