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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-24 16:39:18 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-24 16:39:18 -0700 |
| commit | f1675b88f63b4c279e368d5ec9e6ca48f528024d (patch) | |
| tree | c2f436e5f9350b00d648a68b32bc693294f3ed26 /techlibs/xilinx/drams.txt | |
| parent | c3df895bf464fd651c4d634ecb58ba78ca572f5f (diff) | |
| parent | efd04880dbeb2021c503c82ad962fe8c5d6802d4 (diff) | |
| download | yosys-f1675b88f63b4c279e368d5ec9e6ca48f528024d.tar.gz yosys-f1675b88f63b4c279e368d5ec9e6ca48f528024d.tar.bz2 yosys-f1675b88f63b4c279e368d5ec9e6ca48f528024d.zip | |
Merge remote-tracking branch 'origin/eddie/ram32x1d' into xc7mux
Diffstat (limited to 'techlibs/xilinx/drams.txt')
| -rw-r--r-- | techlibs/xilinx/drams.txt | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/techlibs/xilinx/drams.txt b/techlibs/xilinx/drams.txt index 91632bcee..2613c206c 100644 --- a/techlibs/xilinx/drams.txt +++ b/techlibs/xilinx/drams.txt @@ -1,4 +1,17 @@ +bram $__XILINX_RAM32X1D + init 1 + abits 5 + dbits 1 + groups 2 + ports 1 1 + wrmode 0 1 + enable 0 1 + transp 0 0 + clocks 0 1 + clkpol 0 2 +endbram + bram $__XILINX_RAM64X1D init 1 abits 6 @@ -25,6 +38,13 @@ bram $__XILINX_RAM128X1D clkpol 0 2 endbram +match $__XILINX_RAM32X1D + min bits 3 + min wports 1 + make_outreg + or_next_if_better +endmatch + match $__XILINX_RAM64X1D min bits 5 min wports 1 |