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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-29 11:26:22 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-09-29 11:26:22 -0700 |
| commit | 8474c5b366660153cae03a9de4af8e1ed809856d (patch) | |
| tree | cd157ab16b528565ced19f422ffece1c6110f53e /techlibs/xilinx/dsp_map.v | |
| parent | ce0631c371f69f0132ea9ee4bc8f5ee576dbb1a3 (diff) | |
| parent | b3d8a60cbd94176076f23c4ea6c94ec24e6773e0 (diff) | |
| download | yosys-8474c5b366660153cae03a9de4af8e1ed809856d.tar.gz yosys-8474c5b366660153cae03a9de4af8e1ed809856d.tar.bz2 yosys-8474c5b366660153cae03a9de4af8e1ed809856d.zip | |
Merge pull request #1359 from YosysHQ/xc7dsp
DSP inference for Xilinx (improved for ice40, initial support for ecp5)
Diffstat (limited to 'techlibs/xilinx/dsp_map.v')
| -rw-r--r-- | techlibs/xilinx/dsp_map.v | 49 |
1 files changed, 49 insertions, 0 deletions
diff --git a/techlibs/xilinx/dsp_map.v b/techlibs/xilinx/dsp_map.v new file mode 100644 index 000000000..a4256eb92 --- /dev/null +++ b/techlibs/xilinx/dsp_map.v @@ -0,0 +1,49 @@ +module \$__MUL25X18 (input [24:0] A, input [17:0] B, output [42:0] Y); + parameter A_SIGNED = 0; + parameter B_SIGNED = 0; + parameter A_WIDTH = 0; + parameter B_WIDTH = 0; + parameter Y_WIDTH = 0; + + wire [47:0] P_48; + DSP48E1 #( + // Disable all registers + .ACASCREG(0), + .ADREG(0), + .A_INPUT("DIRECT"), + .ALUMODEREG(0), + .AREG(0), + .BCASCREG(0), + .B_INPUT("DIRECT"), + .BREG(0), + .CARRYINREG(0), + .CARRYINSELREG(0), + .CREG(0), + .DREG(0), + .INMODEREG(0), + .MREG(0), + .OPMODEREG(0), + .PREG(0), + .USE_MULT("MULTIPLY"), + .USE_SIMD("ONE48"), + .USE_DPORT("FALSE") + ) _TECHMAP_REPLACE_ ( + //Data path + .A({{5{A[24]}}, A}), + .B(B), + .C(48'b0), + .D(25'b0), + .P(P_48), + + .INMODE(5'b00000), + .ALUMODE(4'b0000), + .OPMODE(7'b000101), + .CARRYINSEL(3'b000), + + .ACIN(30'b0), + .BCIN(18'b0), + .PCIN(48'b0), + .CARRYIN(1'b0) + ); + assign Y = P_48; +endmodule |