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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-20 17:36:14 -0700 |
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| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-20 17:36:14 -0700 |
| commit | 8f666ebac16a3730aeca4738fc1019e9e7a7e51f (patch) | |
| tree | 52a0769430048af6c925c44cd8bb1c85642d21e6 /techlibs/xilinx/lutrams.txt | |
| parent | 1b5d2de1d4212bd93f9b0ca0d5173e4c8a4dd4e8 (diff) | |
| parent | 33960dd3d84b628f6e5de45c112368dc80626457 (diff) | |
| download | yosys-8f666ebac16a3730aeca4738fc1019e9e7a7e51f.tar.gz yosys-8f666ebac16a3730aeca4738fc1019e9e7a7e51f.tar.bz2 yosys-8f666ebac16a3730aeca4738fc1019e9e7a7e51f.zip | |
Merge remote-tracking branch 'origin/master' into xaig_dff
Diffstat (limited to 'techlibs/xilinx/lutrams.txt')
| -rw-r--r-- | techlibs/xilinx/lutrams.txt | 60 |
1 files changed, 60 insertions, 0 deletions
diff --git a/techlibs/xilinx/lutrams.txt b/techlibs/xilinx/lutrams.txt new file mode 100644 index 000000000..2613c206c --- /dev/null +++ b/techlibs/xilinx/lutrams.txt @@ -0,0 +1,60 @@ + +bram $__XILINX_RAM32X1D + init 1 + abits 5 + dbits 1 + groups 2 + ports 1 1 + wrmode 0 1 + enable 0 1 + transp 0 0 + clocks 0 1 + clkpol 0 2 +endbram + +bram $__XILINX_RAM64X1D + init 1 + abits 6 + dbits 1 + groups 2 + ports 1 1 + wrmode 0 1 + enable 0 1 + transp 0 0 + clocks 0 1 + clkpol 0 2 +endbram + +bram $__XILINX_RAM128X1D + init 1 + abits 7 + dbits 1 + groups 2 + ports 1 1 + wrmode 0 1 + enable 0 1 + transp 0 0 + clocks 0 1 + clkpol 0 2 +endbram + +match $__XILINX_RAM32X1D + min bits 3 + min wports 1 + make_outreg + or_next_if_better +endmatch + +match $__XILINX_RAM64X1D + min bits 5 + min wports 1 + make_outreg + or_next_if_better +endmatch + +match $__XILINX_RAM128X1D + min bits 9 + min wports 1 + make_outreg +endmatch + |