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| author | Eddie Hung <eddie@fpgeh.com> | 2019-12-16 21:48:02 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-12-16 21:48:02 -0800 |
| commit | 9935370ada858da56b5d61a3806768af11565a47 (patch) | |
| tree | 266092bbf791ab2d61b76ee1b63a72ebe8d2f3a3 /techlibs/xilinx/lutrams_map.v | |
| parent | 6d4b6b1e69b2e332d512ed151398bb6bd8e3f3c7 (diff) | |
| parent | 33e6d0558500d14e6711f7fc4ded1ebdb296bcaa (diff) | |
| download | yosys-9935370ada858da56b5d61a3806768af11565a47.tar.gz yosys-9935370ada858da56b5d61a3806768af11565a47.tar.bz2 yosys-9935370ada858da56b5d61a3806768af11565a47.zip | |
Merge pull request #1521 from dh73/diego/memattr
Adding support for Xilinx memory attribute 'block' in single port mode.
Diffstat (limited to 'techlibs/xilinx/lutrams_map.v')
0 files changed, 0 insertions, 0 deletions