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| author | Eddie Hung <eddie@fpgeh.com> | 2019-12-16 21:48:02 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-12-16 21:48:02 -0800 |
| commit | 9935370ada858da56b5d61a3806768af11565a47 (patch) | |
| tree | 266092bbf791ab2d61b76ee1b63a72ebe8d2f3a3 /techlibs | |
| parent | 6d4b6b1e69b2e332d512ed151398bb6bd8e3f3c7 (diff) | |
| parent | 33e6d0558500d14e6711f7fc4ded1ebdb296bcaa (diff) | |
| download | yosys-9935370ada858da56b5d61a3806768af11565a47.tar.gz yosys-9935370ada858da56b5d61a3806768af11565a47.tar.bz2 yosys-9935370ada858da56b5d61a3806768af11565a47.zip | |
Merge pull request #1521 from dh73/diego/memattr
Adding support for Xilinx memory attribute 'block' in single port mode.
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/xilinx/xc7_xcu_brams.txt | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/techlibs/xilinx/xc7_xcu_brams.txt b/techlibs/xilinx/xc7_xcu_brams.txt index b7c893ff7..c63218ae1 100644 --- a/techlibs/xilinx/xc7_xcu_brams.txt +++ b/techlibs/xilinx/xc7_xcu_brams.txt @@ -77,6 +77,8 @@ endbram # https://www.xilinx.com/support/documentation/user_guides/ug473_7Series_Memory_Resources.pdf match $__XILINX_RAMB36_SDP + attribute !ram_style + attribute !logic_block min bits 1024 min efficiency 5 shuffle_enable B @@ -84,7 +86,17 @@ match $__XILINX_RAMB36_SDP or_next_if_better endmatch +match $__XILINX_RAMB36_SDP + attribute ram_style=block ram_block + attribute !logic_block + shuffle_enable B + make_transp + or_next_if_better +endmatch + match $__XILINX_RAMB18_SDP + attribute !ram_style + attribute !logic_block min bits 1024 min efficiency 5 shuffle_enable B @@ -92,7 +104,17 @@ match $__XILINX_RAMB18_SDP or_next_if_better endmatch +match $__XILINX_RAMB18_SDP + attribute ram_style=block ram_block + attribute !logic_block + shuffle_enable B + make_transp + or_next_if_better +endmatch + match $__XILINX_RAMB36_TDP + attribute !ram_style + attribute !logic_block min bits 1024 min efficiency 5 shuffle_enable B @@ -100,9 +122,28 @@ match $__XILINX_RAMB36_TDP or_next_if_better endmatch +match $__XILINX_RAMB36_TDP + attribute ram_style=block ram_block + attribute !logic_block + shuffle_enable B + make_transp + or_next_if_better +endmatch + match $__XILINX_RAMB18_TDP + attribute !ram_style + attribute !logic_block min bits 1024 min efficiency 5 shuffle_enable B make_transp + or_next_if_better +endmatch + +match $__XILINX_RAMB18_TDP + attribute ram_style=block ram_block + attribute !logic_block + shuffle_enable B + make_transp endmatch + |