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| author | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-28 11:17:13 -0800 |
|---|---|---|
| committer | Eddie Hung <eddieh@ece.ubc.ca> | 2019-02-28 11:17:13 -0800 |
| commit | fe4d6898de378260c659dca08398fa434d71f7f0 (patch) | |
| tree | 33a7359d06501631b93febf4b71977cd146e3c92 /techlibs/xilinx/synth_xilinx.cc | |
| parent | 68f38f2ee0e82ac7250e8c4b257e33fd62d21544 (diff) | |
| download | yosys-fe4d6898de378260c659dca08398fa434d71f7f0.tar.gz yosys-fe4d6898de378260c659dca08398fa434d71f7f0.tar.bz2 yosys-fe4d6898de378260c659dca08398fa434d71f7f0.zip | |
synth_xilinx to call shregmap with enable support
Diffstat (limited to 'techlibs/xilinx/synth_xilinx.cc')
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 4e4139154..280c6b729 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -223,7 +223,7 @@ struct SynthXilinxPass : public Pass Pass::call(design, "memory_map"); Pass::call(design, "dffsr2dff"); Pass::call(design, "dff2dffe"); - Pass::call(design, "shregmap -init -params"); + Pass::call(design, "shregmap -init -params -enpol any_or_none"); Pass::call(design, "opt -full"); Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v"); Pass::call(design, "opt -fast"); |