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| author | Eddie Hung <eddie@fpgeh.com> | 2019-04-22 17:58:28 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-22 17:58:28 -0700 |
| commit | 26e461f47da12b79e5b6682f692d81e2721ca0c0 (patch) | |
| tree | a1d62329e21aa28744ea1450e37419985101653c /techlibs/xilinx | |
| parent | 1fa2c36fbd98ff8d748a70c4cb352fa1c6070dae (diff) | |
| download | yosys-26e461f47da12b79e5b6682f692d81e2721ca0c0.tar.gz yosys-26e461f47da12b79e5b6682f692d81e2721ca0c0.tar.bz2 yosys-26e461f47da12b79e5b6682f692d81e2721ca0c0.zip | |
Fix for A_WIDTH == 2 but B_WIDTH==3
Diffstat (limited to 'techlibs/xilinx')
| -rw-r--r-- | techlibs/xilinx/cells_map.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v index 60bc08b48..10dbb8b9a 100644 --- a/techlibs/xilinx/cells_map.v +++ b/techlibs/xilinx/cells_map.v @@ -179,7 +179,7 @@ module \$shiftx (A, B, Y); assign A_i[i] = A[i*2]; \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH((A_WIDTH+1'd1)/2'd2), .B_WIDTH(B_WIDTH-1'd1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A_i), .B(B[B_WIDTH-1:1]), .Y(Y)); end - else if (B_WIDTH < 3) begin + else if (B_WIDTH < 3 || A_WIDTH == 2**2) begin wire _TECHMAP_FAIL_ = 1; end else if (B_WIDTH == 3) begin |