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| author | Miodrag Milanović <mmicko@gmail.com> | 2020-01-14 19:19:32 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-01-14 19:19:32 +0100 |
| commit | 9fbeb57bbdb98265b541d7a62213e83de63c8a1a (patch) | |
| tree | a095bc5fbcfe5a3007fc17b928887e4b9fe2cefa /techlibs/xilinx | |
| parent | ca2f3db53f3f330d283079bf44b3cef6b7f197be (diff) | |
| parent | ccfe1e5909ba6093e49ebdfaa1aac6c4aa267036 (diff) | |
| download | yosys-9fbeb57bbdb98265b541d7a62213e83de63c8a1a.tar.gz yosys-9fbeb57bbdb98265b541d7a62213e83de63c8a1a.tar.bz2 yosys-9fbeb57bbdb98265b541d7a62213e83de63c8a1a.zip | |
Merge pull request #1623 from YosysHQ/mmicko/edif_attr
Export wire properties in EDIF
Diffstat (limited to 'techlibs/xilinx')
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index d916093dc..77be8299c 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -518,7 +518,7 @@ struct SynthXilinxPass : public ScriptPass techmap_args += " -map +/xilinx/arith_map.v"; if (vpr) techmap_args += " -D _EXPLICIT_CARRY"; - else if (abc9) + else techmap_args += " -D _CLB_CARRY"; } run("techmap " + techmap_args); |