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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-31 02:32:00 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-31 02:32:00 +0200 |
| commit | 1202f7aa4bb0f9afde157ebc4701d64e7e38abd8 (patch) | |
| tree | d1a4bb9dfe62ac911ca4751a98b3b63dba22af40 /techlibs | |
| parent | 6ca0c569d92883b6eac1725204de90aee4af31bc (diff) | |
| download | yosys-1202f7aa4bb0f9afde157ebc4701d64e7e38abd8.tar.gz yosys-1202f7aa4bb0f9afde157ebc4701d64e7e38abd8.tar.bz2 yosys-1202f7aa4bb0f9afde157ebc4701d64e7e38abd8.zip | |
Renamed "stdcells.v" to "techmap.v"
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/common/Makefile.inc | 6 | ||||
| -rw-r--r-- | techlibs/common/simcells.v | 2 | ||||
| -rw-r--r-- | techlibs/common/techmap.v (renamed from techlibs/common/stdcells.v) | 0 |
3 files changed, 6 insertions, 2 deletions
diff --git a/techlibs/common/Makefile.inc b/techlibs/common/Makefile.inc index a76d1a079..2be27b920 100644 --- a/techlibs/common/Makefile.inc +++ b/techlibs/common/Makefile.inc @@ -5,7 +5,7 @@ techlibs/common/blackbox.v: techlibs/common/blackbox.sed techlibs/common/simlib. $(P) cat techlibs/common/simlib.v techlibs/common/simcells.v | $(SED) -rf techlibs/common/blackbox.sed > techlibs/common/blackbox.v.new $(Q) mv techlibs/common/blackbox.v.new techlibs/common/blackbox.v -EXTRA_TARGETS += share/simlib.v share/simcells.v share/blackbox.v share/pmux2mux.v +EXTRA_TARGETS += share/simlib.v share/simcells.v share/techmap.v share/blackbox.v share/pmux2mux.v share/simlib.v: techlibs/common/simlib.v $(P) mkdir -p share @@ -15,6 +15,10 @@ share/simcells.v: techlibs/common/simcells.v $(P) mkdir -p share $(Q) cp techlibs/common/simcells.v share/simcells.v +share/techmap.v: techlibs/common/techmap.v + $(P) mkdir -p share + $(Q) cp techlibs/common/techmap.v share/techmap.v + share/blackbox.v: techlibs/common/blackbox.v $(P) mkdir -p share $(Q) cp techlibs/common/blackbox.v share/blackbox.v diff --git a/techlibs/common/simcells.v b/techlibs/common/simcells.v index 5ecec7891..d492c2f15 100644 --- a/techlibs/common/simcells.v +++ b/techlibs/common/simcells.v @@ -21,7 +21,7 @@ * * This verilog library contains simple simulation models for the internal * logic cells ($_INV_ , $_AND_ , ...) that are generated by the default technology - * mapper (see "stdcells.v" in this directory) and expected by the "abc" pass. + * mapper (see "techmap.v" in this directory) and expected by the "abc" pass. * */ diff --git a/techlibs/common/stdcells.v b/techlibs/common/techmap.v index 54652868a..54652868a 100644 --- a/techlibs/common/stdcells.v +++ b/techlibs/common/techmap.v |