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| author | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-10-18 20:46:49 -0700 |
|---|---|---|
| committer | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-10-18 20:46:49 -0700 |
| commit | 1cca1563c64cd521a384a5df404dbccb3e06cb5c (patch) | |
| tree | bf3776bff22c07bde74629179c99626f0f4d642d /techlibs | |
| parent | e78fa157a3decfc6e595089c7d73b9cca785b252 (diff) | |
| download | yosys-1cca1563c64cd521a384a5df404dbccb3e06cb5c.tar.gz yosys-1cca1563c64cd521a384a5df404dbccb3e06cb5c.tar.bz2 yosys-1cca1563c64cd521a384a5df404dbccb3e06cb5c.zip | |
Fixed typo in last commit
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/greenpak4/cells_sim.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v index 76bf058d2..80746be0f 100644 --- a/techlibs/greenpak4/cells_sim.v +++ b/techlibs/greenpak4/cells_sim.v @@ -308,7 +308,7 @@ endmodule module GP_PGEN(input wire nRST, input wire CLK, output reg OUT); initial OUT = 0; parameter PATTERN_DATA = 16'h0; - parameter PATTERN_LEN = 4'd16; + parameter PATTERN_LEN = 5'd16; reg[3:0] count = 0; always @(posedge CLK) begin |