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| author | Eddie Hung <eddie@fpgeh.com> | 2020-04-22 14:37:27 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-04-22 14:37:27 -0700 |
| commit | 274098cce6133dfb9a5b0ad013e55119cb1741cf (patch) | |
| tree | 1055095be1f5ad79d6fde0dbc265f2f034a68c1c /techlibs | |
| parent | cf14e186eb6c89696cd1db4b36697a4e80b6884a (diff) | |
| parent | 7f33a0294b7e6a299033cb4ee19bd86317737c08 (diff) | |
| download | yosys-274098cce6133dfb9a5b0ad013e55119cb1741cf.tar.gz yosys-274098cce6133dfb9a5b0ad013e55119cb1741cf.tar.bz2 yosys-274098cce6133dfb9a5b0ad013e55119cb1741cf.zip | |
Merge pull request #1983 from YosysHQ/eddie/use_default_param
Cleanup use of hard-coded default parameters in light of #1945
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/ecp5/ecp5_ffinit.cc | 12 | ||||
| -rw-r--r-- | techlibs/ecp5/ecp5_gsr.cc | 6 |
2 files changed, 6 insertions, 12 deletions
diff --git a/techlibs/ecp5/ecp5_ffinit.cc b/techlibs/ecp5/ecp5_ffinit.cc index e85bee64e..ba72bd0c6 100644 --- a/techlibs/ecp5/ecp5_ffinit.cc +++ b/techlibs/ecp5/ecp5_ffinit.cc @@ -106,9 +106,7 @@ struct Ecp5FfinitPass : public Pass { SigBit bit_d = sigmap(sig_d[0]); SigBit bit_q = sigmap(sig_q[0]); - std::string regset = "RESET"; - if (cell->hasParam(ID(REGSET))) - regset = cell->getParam(ID(REGSET)).decode_string(); + std::string regset = cell->getParam(ID(REGSET)).decode_string(); State resetState; if (regset == "SET") resetState = State::S1; @@ -135,9 +133,7 @@ struct Ecp5FfinitPass : public Pass { } if (GetSize(sig_lsr) >= 1 && sig_lsr[0] != State::S0) { - std::string srmode = "LSR_OVER_CE"; - if (cell->hasParam(ID(SRMODE))) - srmode = cell->getParam(ID(SRMODE)).decode_string(); + std::string srmode = cell->getParam(ID(SRMODE)).decode_string(); if (srmode == "ASYNC") { log("Async reset value %c for FF cell %s inconsistent with init value %c.\n", resetState != State::S0 ? '1' : '0', log_id(cell), val != State::S0 ? '1' : '0'); @@ -154,9 +150,7 @@ struct Ecp5FfinitPass : public Pass { cell->setPort(ID(LSR), State::S0); if(cell->hasPort(ID(CE))) { - std::string cemux = "CE"; - if (cell->hasParam(ID(CEMUX))) - cemux = cell->getParam(ID(CEMUX)).decode_string(); + std::string cemux = cell->getParam(ID(CEMUX)).decode_string(); SigSpec sig_ce = cell->getPort(ID(CE)); if (GetSize(sig_ce) >= 1) { SigBit bit_ce = sigmap(sig_ce[0]); diff --git a/techlibs/ecp5/ecp5_gsr.cc b/techlibs/ecp5/ecp5_gsr.cc index d1503f71f..1c69e1d79 100644 --- a/techlibs/ecp5/ecp5_gsr.cc +++ b/techlibs/ecp5/ecp5_gsr.cc @@ -81,7 +81,7 @@ struct Ecp5GsrPass : public Pass { for (auto cell : module->selected_cells()) { - if (!cell->hasParam(ID(GSR)) || cell->getParam(ID(GSR)).decode_string() != "AUTO") + if (cell->getParam(ID(GSR)).decode_string() != "AUTO") continue; bool gsren = found_gsr; @@ -114,9 +114,9 @@ struct Ecp5GsrPass : public Pass { { if (cell->type != ID(TRELLIS_FF)) continue; - if (!cell->hasParam(ID(GSR)) || cell->getParam(ID(GSR)).decode_string() != "ENABLED") + if (cell->getParam(ID(GSR)).decode_string() != "ENABLED") continue; - if (!cell->hasParam(ID(SRMODE)) || cell->getParam(ID(SRMODE)).decode_string() != "ASYNC") + if (cell->getParam(ID(SRMODE)).decode_string() != "ASYNC") continue; SigSpec sig_lsr = cell->getPort(ID(LSR)); if (GetSize(sig_lsr) < 1) |