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| author | Clifford Wolf <clifford@clifford.at> | 2017-09-01 12:33:47 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2017-09-01 12:33:47 +0200 |
| commit | 307dc55d65f9b9c07c10f6043ce0f165aac3852e (patch) | |
| tree | 3c48790ce444bc2de95d20b01181f6d871e53fbb /techlibs | |
| parent | 85303334396904edfa0d77852b77c64870468f79 (diff) | |
| parent | 8a66bd30c67c753149a195b951a3191d8e5e3304 (diff) | |
| download | yosys-307dc55d65f9b9c07c10f6043ce0f165aac3852e.tar.gz yosys-307dc55d65f9b9c07c10f6043ce0f165aac3852e.tar.bz2 yosys-307dc55d65f9b9c07c10f6043ce0f165aac3852e.zip | |
Merge branch 'ChipScan-master'
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/greenpak4/cells_sim_digital.v | 68 |
1 files changed, 34 insertions, 34 deletions
diff --git a/techlibs/greenpak4/cells_sim_digital.v b/techlibs/greenpak4/cells_sim_digital.v index 043cd18d4..b87795ceb 100644 --- a/techlibs/greenpak4/cells_sim_digital.v +++ b/techlibs/greenpak4/cells_sim_digital.v @@ -147,7 +147,15 @@ module GP_COUNT14_ADV(input CLK, input RST, output reg OUT, "RISING": begin always @(posedge CLK, posedge RST) begin - if(KEEP) begin + //Resets + if(RST) begin + if(RESET_VALUE == "ZERO") + count <= 0; + else + count <= COUNT_TO; + end + + else if(KEEP) begin end else if(UP) begin count <= count + 1'd1; @@ -161,21 +169,21 @@ module GP_COUNT14_ADV(input CLK, input RST, output reg OUT, count <= COUNT_TO; end + end + end + + "FALLING": begin + always @(posedge CLK, negedge RST) begin + //Resets - if(RST) begin + if(!RST) begin if(RESET_VALUE == "ZERO") count <= 0; else count <= COUNT_TO; end - end - end - - "FALLING": begin - always @(posedge CLK, negedge RST) begin - - if(KEEP) begin + else if(KEEP) begin end else if(UP) begin count <= count + 1'd1; @@ -189,14 +197,6 @@ module GP_COUNT14_ADV(input CLK, input RST, output reg OUT, count <= COUNT_TO; end - //Resets - if(!RST) begin - if(RESET_VALUE == "ZERO") - count <= 0; - else - count <= COUNT_TO; - end - end end @@ -286,8 +286,16 @@ module GP_COUNT8_ADV(input CLK, input RST, output reg OUT, "RISING": begin always @(posedge CLK, posedge RST) begin + //Resets + if(RST) begin + if(RESET_VALUE == "ZERO") + count <= 0; + else + count <= COUNT_TO; + end + //Main counter - if(KEEP) begin + else if(KEEP) begin end else if(UP) begin count <= count + 1'd1; @@ -301,22 +309,22 @@ module GP_COUNT8_ADV(input CLK, input RST, output reg OUT, count <= COUNT_TO; end + end + end + + "FALLING": begin + always @(posedge CLK, negedge RST) begin + //Resets - if(RST) begin + if(!RST) begin if(RESET_VALUE == "ZERO") count <= 0; else count <= COUNT_TO; end - end - end - - "FALLING": begin - always @(posedge CLK, negedge RST) begin - //Main counter - if(KEEP) begin + else if(KEEP) begin end else if(UP) begin count <= count + 1'd1; @@ -330,14 +338,6 @@ module GP_COUNT8_ADV(input CLK, input RST, output reg OUT, count <= COUNT_TO; end - //Resets - if(!RST) begin - if(RESET_VALUE == "ZERO") - count <= 0; - else - count <= COUNT_TO; - end - end end |