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| author | Clifford Wolf <clifford@clifford.at> | 2014-08-07 16:14:38 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-08-07 16:14:38 +0200 |
| commit | 312ee00c9e279a91f336acef26dd064c25f42ed5 (patch) | |
| tree | e9fc1d70b7677ef6961f03fa3fff0f846bdc8aaf /techlibs | |
| parent | d259abbda2b9d568228dc8d0bed2d0b0d88d7b4f (diff) | |
| download | yosys-312ee00c9e279a91f336acef26dd064c25f42ed5.tar.gz yosys-312ee00c9e279a91f336acef26dd064c25f42ed5.tar.bz2 yosys-312ee00c9e279a91f336acef26dd064c25f42ed5.zip | |
Added adff2dff.v (for techmap -share_map)
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/common/Makefile.inc | 6 | ||||
| -rw-r--r-- | techlibs/common/adff2dff.v | 27 |
2 files changed, 32 insertions, 1 deletions
diff --git a/techlibs/common/Makefile.inc b/techlibs/common/Makefile.inc index 2be27b920..461c1cb44 100644 --- a/techlibs/common/Makefile.inc +++ b/techlibs/common/Makefile.inc @@ -5,7 +5,7 @@ techlibs/common/blackbox.v: techlibs/common/blackbox.sed techlibs/common/simlib. $(P) cat techlibs/common/simlib.v techlibs/common/simcells.v | $(SED) -rf techlibs/common/blackbox.sed > techlibs/common/blackbox.v.new $(Q) mv techlibs/common/blackbox.v.new techlibs/common/blackbox.v -EXTRA_TARGETS += share/simlib.v share/simcells.v share/techmap.v share/blackbox.v share/pmux2mux.v +EXTRA_TARGETS += share/simlib.v share/simcells.v share/techmap.v share/blackbox.v share/pmux2mux.v share/adff2dff.v share/simlib.v: techlibs/common/simlib.v $(P) mkdir -p share @@ -27,3 +27,7 @@ share/pmux2mux.v: techlibs/common/pmux2mux.v $(P) mkdir -p share $(Q) cp techlibs/common/pmux2mux.v share/pmux2mux.v +share/adff2dff.v: techlibs/common/adff2dff.v + $(P) mkdir -p share + $(Q) cp techlibs/common/adff2dff.v share/adff2dff.v + diff --git a/techlibs/common/adff2dff.v b/techlibs/common/adff2dff.v new file mode 100644 index 000000000..86744d415 --- /dev/null +++ b/techlibs/common/adff2dff.v @@ -0,0 +1,27 @@ +(* techmap_celltype = "$adff" *) +module adff2dff (CLK, ARST, D, Q); + parameter WIDTH = 1; + parameter CLK_POLARITY = 1; + parameter ARST_POLARITY = 1; + parameter ARST_VALUE = 0; + + input CLK, ARST; + input [WIDTH-1:0] D; + output reg [WIDTH-1:0] Q; + wire reg [WIDTH-1:0] NEXT_Q; + + wire [1023:0] _TECHMAP_DO_ = "proc;;"; + + always @* + if (ARST == ARST_POLARITY) + NEXT_Q <= ARST_VALUE; + else + NEXT_Q <= D; + + if (CLK_POLARITY) + always @(posedge CLK) + Q <= NEXT_Q; + else + always @(negedge CLK) + Q <= NEXT_Q; +endmodule |