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| author | Eddie Hung <eddie@fpgeh.com> | 2020-02-14 11:41:43 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-02-27 10:17:29 -0800 |
| commit | 3ea5506f812879c0ecf66431efde002493e11bdf (patch) | |
| tree | 4c6607a3ba89fd5aff5fffb8f84828f9cb53d351 /techlibs | |
| parent | cda4acb544614711b2c187e93f515bfc43ca8da1 (diff) | |
| download | yosys-3ea5506f812879c0ecf66431efde002493e11bdf.tar.gz yosys-3ea5506f812879c0ecf66431efde002493e11bdf.tar.bz2 yosys-3ea5506f812879c0ecf66431efde002493e11bdf.zip | |
abc9_ops: use TimingInfo for -prep_{lut,box} too
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/xilinx/abc9_model.v | 17 |
1 files changed, 10 insertions, 7 deletions
diff --git a/techlibs/xilinx/abc9_model.v b/techlibs/xilinx/abc9_model.v index 8e2a05ceb..f83e97a2a 100644 --- a/techlibs/xilinx/abc9_model.v +++ b/techlibs/xilinx/abc9_model.v @@ -69,6 +69,7 @@ endmodule (* abc9_box *) module \$__ABC9_RAM6 (input A, input [5:0] S, output Y); specify + (A => Y) = 0; (S[0] => Y) = 642; (S[1] => Y) = 631; (S[2] => Y) = 472; @@ -81,13 +82,15 @@ endmodule (* abc9_box *) module \$__ABC9_RAM7 (input A, input [6:0] S, output Y); specify - (S[0] => Y) = 1028; - (S[1] => Y) = 1017; - (S[2] => Y) = 858; - (S[3] => Y) = 793; - (S[4] => Y) = 624; - (S[5] => Y) = 513; - (S[6] => Y) = 464; + (A => Y) = 0; + // https://github.com/SymbiFlow/prjxray-db/blob/1c85daf1b115da4d27ca83c6b89f53a94de39748/artix7/timings/slicel.sdf#L867 + (S[0] => Y) = 642 + 223 /* to cross F7BMUX */ + 174 /* CMUX */; + (S[1] => Y) = 631 + 223 /* to cross F7BMUX */ + 174 /* CMUX */; + (S[2] => Y) = 472 + 223 /* to cross F7BMUX */ + 174 /* CMUX */; + (S[3] => Y) = 407 + 223 /* to cross F7BMUX */ + 174 /* CMUX */; + (S[4] => Y) = 238 + 223 /* to cross F7BMUX */ + 174 /* CMUX */; + (S[5] => Y) = 127 + 223 /* to cross F7BMUX */ + 174 /* CMUX */; + (S[6] => Y) = 0 + 296 /* to select F7BMUX */ + 174 /* CMUX */; endspecify endmodule |