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| author | Andrew Zonenberg <azonenberg@drawersteak.com> | 2017-08-07 15:49:30 -0700 |
|---|---|---|
| committer | Andrew Zonenberg <azonenberg@drawersteak.com> | 2017-08-14 10:45:39 -0700 |
| commit | 4504dd78e9bba5b768fbc3a91e006c5679366e15 (patch) | |
| tree | 797c785ba3d6335234177c708650dd6e5b6fdaf2 /techlibs | |
| parent | 60dd5dba7ba07b1992123681b37d6ffa6dd2dae4 (diff) | |
| download | yosys-4504dd78e9bba5b768fbc3a91e006c5679366e15.tar.gz yosys-4504dd78e9bba5b768fbc3a91e006c5679366e15.tar.bz2 yosys-4504dd78e9bba5b768fbc3a91e006c5679366e15.zip | |
Fixed typo in COUNT8 model
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/greenpak4/cells_sim_digital.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/greenpak4/cells_sim_digital.v b/techlibs/greenpak4/cells_sim_digital.v index f8ab5bf37..ccf9840c7 100644 --- a/techlibs/greenpak4/cells_sim_digital.v +++ b/techlibs/greenpak4/cells_sim_digital.v @@ -61,7 +61,7 @@ module GP_COUNT8( count <= COUNT_TO; if(RST) - count <= COUNT_0; + count <= 0; end end @@ -72,7 +72,7 @@ module GP_COUNT8( count <= COUNT_TO; if(!RST) - count <= COUNT_0; + count <= 0; end end |