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| author | Clifford Wolf <clifford@clifford.at> | 2019-04-22 18:19:02 +0200 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2019-04-22 18:19:02 +0200 |
| commit | 4ad0ea5c3c325dc639829f6c6836353044585af5 (patch) | |
| tree | b7cc4109abee651d2a2045109017708e03ced040 /techlibs | |
| parent | c0f9a74b121dd19e359038b6f6f76be0ffe3cc38 (diff) | |
| download | yosys-4ad0ea5c3c325dc639829f6c6836353044585af5.tar.gz yosys-4ad0ea5c3c325dc639829f6c6836353044585af5.tar.bz2 yosys-4ad0ea5c3c325dc639829f6c6836353044585af5.zip | |
Determine correct signedness and expression width in for loop unrolling, fixes #370
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'techlibs')
0 files changed, 0 insertions, 0 deletions