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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-27 16:11:39 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-27 16:11:39 -0700 |
| commit | 4daa74679779a45542b36c1f3630bd1fbae9ec7b (patch) | |
| tree | ececabc9459dc32ddb982f790cebe74e74575ac5 /techlibs | |
| parent | 9398921af1d21b47aa291d240a1f274418adcaf2 (diff) | |
| download | yosys-4daa74679779a45542b36c1f3630bd1fbae9ec7b.tar.gz yosys-4daa74679779a45542b36c1f3630bd1fbae9ec7b.tar.bz2 yosys-4daa74679779a45542b36c1f3630bd1fbae9ec7b.zip | |
Remove noise from ice40/cells_sim.v
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/ice40/cells_sim.v | 5 |
1 files changed, 0 insertions, 5 deletions
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v index c7e4101e1..b746ba4e5 100644 --- a/techlibs/ice40/cells_sim.v +++ b/techlibs/ice40/cells_sim.v @@ -144,12 +144,8 @@ endmodule // Positive Edge SiliconBlue FF Cells module SB_DFF (output `SB_DFF_REG, input C, D); -`ifndef _ABC always @(posedge C) Q <= D; -`else - always @* Q <= D; -`endif endmodule module SB_DFFE (output `SB_DFF_REG, input C, E, D); @@ -896,7 +892,6 @@ module SB_WARMBOOT ( ); endmodule -(* nomem2reg *) module SB_SPRAM256KA ( input [13:0] ADDRESS, input [15:0] DATAIN, |