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| author | whitequark <whitequark@whitequark.org> | 2019-07-08 12:48:50 +0000 |
|---|---|---|
| committer | whitequark <whitequark@whitequark.org> | 2019-07-08 12:48:50 +0000 |
| commit | 55c1f4027794a89971055b705254832b189a1c83 (patch) | |
| tree | 411b0132ec7cdb88b314b6eb79de2c1c5593dd96 /techlibs | |
| parent | b1f400aeb8de657d5fa28c153df14246378df2b1 (diff) | |
| download | yosys-55c1f4027794a89971055b705254832b189a1c83.tar.gz yosys-55c1f4027794a89971055b705254832b189a1c83.tar.bz2 yosys-55c1f4027794a89971055b705254832b189a1c83.zip | |
verilog_backend: dump attributes on CaseRule, as comments.
Attributes are not permitted in that position by Verilog grammar.
Diffstat (limited to 'techlibs')
0 files changed, 0 insertions, 0 deletions