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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2022-01-30 20:48:50 +0100 |
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| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2022-01-31 01:08:41 +0100 |
| commit | 56e7791760ce67cb1831691460b50bf73a4f5117 (patch) | |
| tree | add3d8b2488630378d8152b4c305ff99bd27b75f /techlibs | |
| parent | 07a657fb0ca08012af3de410520458af255b1097 (diff) | |
| download | yosys-56e7791760ce67cb1831691460b50bf73a4f5117.tar.gz yosys-56e7791760ce67cb1831691460b50bf73a4f5117.tar.bz2 yosys-56e7791760ce67cb1831691460b50bf73a4f5117.zip | |
verilog backend: Emit a `wire` for ports as well.
Fixes #3177.
Diffstat (limited to 'techlibs')
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