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| author | whitequark <whitequark@whitequark.org> | 2019-07-08 15:11:29 +0000 |
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| committer | whitequark <whitequark@whitequark.org> | 2019-07-08 15:11:29 +0000 |
| commit | 628437b01cd37b95c020b2f4c4e2f2d8f0e9bf8b (patch) | |
| tree | a7ee0c5daa8701c505665dbf936aa0c957b83fdb /techlibs | |
| parent | 48655dfb8b4dda7607ed7a790eb5f6bce5c27d38 (diff) | |
| download | yosys-628437b01cd37b95c020b2f4c4e2f2d8f0e9bf8b.tar.gz yosys-628437b01cd37b95c020b2f4c4e2f2d8f0e9bf8b.tar.bz2 yosys-628437b01cd37b95c020b2f4c4e2f2d8f0e9bf8b.zip | |
verilog_backend: dump attributes on SwitchRule.
This appears to be an omission.
Diffstat (limited to 'techlibs')
0 files changed, 0 insertions, 0 deletions