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| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-17 19:25:59 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-01-17 19:25:59 -0800 |
| commit | 67c6bf0b6b8a5a2d03a7e64b3baa5c1d3021e6d1 (patch) | |
| tree | 10fadff3585ad4c56a2a0fcefcf44f9e6e36eefe /techlibs | |
| parent | 2bda51ac34d6f542d1d6477eecede1d6527c10b3 (diff) | |
| parent | 6a163b5ddd378ba847054ad9226af8ca569c977a (diff) | |
| download | yosys-67c6bf0b6b8a5a2d03a7e64b3baa5c1d3021e6d1.tar.gz yosys-67c6bf0b6b8a5a2d03a7e64b3baa5c1d3021e6d1.tar.bz2 yosys-67c6bf0b6b8a5a2d03a7e64b3baa5c1d3021e6d1.zip | |
Merge pull request #1645 from YosysHQ/eddie/fix1644
{ice40,xilinx}_dsp: improve robustess
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/ice40/synth_ice40.cc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index 121bcff1f..d92e40726 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -273,7 +273,8 @@ struct SynthIce40Pass : public ScriptPass run("opt_expr"); run("opt_clean"); if (help_mode || dsp) { - run("memory_dff"); + run("memory_dff"); // ice40_dsp will merge registers, reserve memory port registers first + run("wreduce t:$mul"); run("techmap -map +/mul2dsp.v -map +/ice40/dsp_map.v -D DSP_A_MAXWIDTH=16 -D DSP_B_MAXWIDTH=16 " "-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_Y_MINWIDTH=11 " "-D DSP_NAME=$__MUL16X16", "(if -dsp)"); |