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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-08 19:26:43 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-07-08 19:26:43 -0700 |
| commit | 7600ffe4bdf064f71f6380563060f85877ce481e (patch) | |
| tree | 5be14494e9c40e4b6f59c72f8f6317e92c3caacc /techlibs | |
| parent | 41d7d9d24b8ba7fd84dd72b27eb9aede10b8ef15 (diff) | |
| parent | ede1ef61c5761f1e41820f16775d9afb2b75c1c8 (diff) | |
| download | yosys-7600ffe4bdf064f71f6380563060f85877ce481e.tar.gz yosys-7600ffe4bdf064f71f6380563060f85877ce481e.tar.bz2 yosys-7600ffe4bdf064f71f6380563060f85877ce481e.zip | |
Merge branch 'master' of github.com:YosysHQ/yosys
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/intel/synth_intel.cc | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/techlibs/intel/synth_intel.cc b/techlibs/intel/synth_intel.cc index 639cba2c2..09c9ba3af 100644 --- a/techlibs/intel/synth_intel.cc +++ b/techlibs/intel/synth_intel.cc @@ -48,6 +48,8 @@ struct SynthIntelPass : public ScriptPass { log(" -vqm <file>\n"); log(" write the design to the specified Verilog Quartus Mapping File. Writing of an\n"); log(" output file is omitted if this parameter is not specified.\n"); + log(" Note that this backend has not been tested and is likely incompatible\n"); + log(" with recent versions of Quartus.\n"); log("\n"); log(" -vpr <file>\n"); log(" write BLIF files for VPR flow experiments. The synthesized BLIF output file is not\n"); @@ -108,6 +110,7 @@ struct SynthIntelPass : public ScriptPass { } if (args[argidx] == "-vqm" && argidx + 1 < args.size()) { vout_file = args[++argidx]; + log_warning("The Quartus backend has not been tested recently and is likely incompatible with modern versions of Quartus.\n"); continue; } if (args[argidx] == "-vpr" && argidx + 1 < args.size()) { |