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| author | Eddie Hung <eddie@fpgeh.com> | 2019-04-26 14:51:37 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-26 14:51:37 -0700 |
| commit | 8469d9fe9ff0a819c6b67aa6121cfd01cd1d0665 (patch) | |
| tree | a096720a12d326a4e59acb54d70408c150cc0179 /techlibs | |
| parent | 4473fd15020cc186fde71eadc2325f69c92ae7ac (diff) | |
| download | yosys-8469d9fe9ff0a819c6b67aa6121cfd01cd1d0665.tar.gz yosys-8469d9fe9ff0a819c6b67aa6121cfd01cd1d0665.tar.bz2 yosys-8469d9fe9ff0a819c6b67aa6121cfd01cd1d0665.zip | |
Missing newline
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index f65ae87f5..b6b22284c 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -139,7 +139,7 @@ struct SynthXilinxPass : public Pass log(" abc -luts 2:2,3,6:5,10,20 [-dff]\n"); log(" clean\n"); log(" shregmap -minlen 3 -init -params -enpol any_or_none (without '-nosrl' only)\n"); - log(" techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v -map +/xilinx/cells_map.v"); + log(" techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v -map +/xilinx/cells_map.v\n"); log(" dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT \\\n"); log(" -ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT\n"); log("\n"); |