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| author | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-12-05 23:49:06 -0800 |
|---|---|---|
| committer | Andrew Zonenberg <azonenberg@drawersteak.com> | 2016-12-05 23:49:06 -0800 |
| commit | 8767cdcac95d30a454ba2bdd7c0d81083d3215ec (patch) | |
| tree | c18266ad2b13fb98b9ae66e4dc5151412d9c544c /techlibs | |
| parent | 981f01430190aeba2c27dd516cefb5730063fcc7 (diff) | |
| download | yosys-8767cdcac95d30a454ba2bdd7c0d81083d3215ec.tar.gz yosys-8767cdcac95d30a454ba2bdd7c0d81083d3215ec.tar.bz2 yosys-8767cdcac95d30a454ba2bdd7c0d81083d3215ec.zip | |
Added GP_DLATCH and GP_DLATCHI
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/greenpak4/cells_sim.v | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v index 1b3a66038..a59d17154 100644 --- a/techlibs/greenpak4/cells_sim.v +++ b/techlibs/greenpak4/cells_sim.v @@ -240,6 +240,24 @@ module GP_DFFSRI(input D, CLK, nSR, output reg nQ); end endmodule +module GP_DLATCH(input D, input nCLK, output reg Q); + parameter [0:0] INIT = 1'bx; + initial Q = INIT; + always @(*) begin + if(!nCLK) + Q <= D; + end +endmodule + +module GP_DLATCHI(input D, input nCLK, output reg Q); + parameter [0:0] INIT = 1'bx; + initial Q = INIT; + always @(*) begin + if(!nCLK) + Q <= ~D; + end +endmodule + module GP_DLATCHR(input D, input nCLK, input nRST, output reg Q); parameter [0:0] INIT = 1'bx; initial Q = INIT; |