Merge branch 'master' of github.com:cliffordwolf/yosys

1 files changed, 26 insertions, 0 deletions

diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v
index be8e66c66..67f00f3a4 100644
--- a/techlibs/greenpak4/cells_sim.v
+++ b/techlibs/greenpak4/cells_sim.v
@@ -94,6 +94,32 @@ module GP_COUNT14(input CLK, input wire RST, output reg OUT);
 
 endmodule
 
+module GP_COUNT8_ADV(input CLK, input RST, output reg OUT,
+                     input UP, input KEEP);
+
+	parameter RESET_MODE 	= "RISING";
+	parameter RESET_VALUE   = "ZERO";
+
+	parameter COUNT_TO		= 8'h1;
+	parameter CLKIN_DIVIDE	= 1;
+
+	//more complex hard IP blocks are not supported for simulation yet
+
+endmodule
+
+module GP_COUNT14_ADV(input CLK, input RST, output reg OUT,
+                      input UP, input KEEP);
+
+	parameter RESET_MODE 	= "RISING";
+	parameter RESET_VALUE   = "ZERO";
+
+	parameter COUNT_TO		= 14'h1;
+	parameter CLKIN_DIVIDE	= 1;
+
+	//more complex hard IP blocks are not supported for simulation yet
+
+endmodule
+
 module GP_DELAY(input IN, output reg OUT);
 	
 	parameter DELAY_STEPS = 1;