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| author | Clifford Wolf <clifford@clifford.at> | 2019-02-28 20:27:27 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-02-28 20:27:27 -0800 |
| commit | a82a7eb42e4d7059ff6efa89b1013134015e118a (patch) | |
| tree | c3df467bd0600ec04e1531414841f2f967c95652 /techlibs | |
| parent | b84febafd75bc66d64cdc573265e086800b3e420 (diff) | |
| parent | cd2902ab1fec57503320e32ba5620c6487f9cb85 (diff) | |
| download | yosys-a82a7eb42e4d7059ff6efa89b1013134015e118a.tar.gz yosys-a82a7eb42e4d7059ff6efa89b1013134015e118a.tar.bz2 yosys-a82a7eb42e4d7059ff6efa89b1013134015e118a.zip | |
Merge pull request #836 from elmsfu/ice40_2bit_ram_rw_mode
ice40: use 2 bits for READ/WRITE MODE for SB_RAM map
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/ice40/brams_map.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/ice40/brams_map.v b/techlibs/ice40/brams_map.v index 19a61d73b..ad3bccd21 100644 --- a/techlibs/ice40/brams_map.v +++ b/techlibs/ice40/brams_map.v @@ -7,8 +7,8 @@ module \$__ICE40_RAM4K ( input [10:0] WADDR, input [15:0] MASK, WDATA ); - parameter integer READ_MODE = 0; - parameter integer WRITE_MODE = 0; + parameter [1:0] READ_MODE = 0; + parameter [1:0] WRITE_MODE = 0; parameter [0:0] NEGCLK_R = 0; parameter [0:0] NEGCLK_W = 0; |