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| author | Eddie Hung <eddie@fpgeh.com> | 2020-04-20 10:30:10 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-04-20 10:30:10 -0700 |
| commit | a998a4155d0e8a109bae80c3be24ed8465378b46 (patch) | |
| tree | c5082758b19d007a83ff16df53163c37c4aad887 /techlibs | |
| parent | ae115fa3aac9acf7534b3f7c08afaa1b86bfc4ad (diff) | |
| download | yosys-a998a4155d0e8a109bae80c3be24ed8465378b46.tar.gz yosys-a998a4155d0e8a109bae80c3be24ed8465378b46.tar.bz2 yosys-a998a4155d0e8a109bae80c3be24ed8465378b46.zip | |
xilinx/ecp5: disable abc9's "&mfs" optimisation
Can sometimes fire an assertion, e.g. #1962
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/ecp5/synth_ecp5.cc | 2 | ||||
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 2 |
2 files changed, 4 insertions, 0 deletions
diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc index ab740ea0d..317947978 100644 --- a/techlibs/ecp5/synth_ecp5.cc +++ b/techlibs/ecp5/synth_ecp5.cc @@ -324,6 +324,8 @@ struct SynthEcp5Pass : public ScriptPass if (abc9) { run("read_verilog -icells -lib -specify +/abc9_model.v +/ecp5/abc9_model.v"); + if (!help_mode && !active_design->scratchpad.count("abc9.nomfs")) + active_design->scratchpad_set_bool("abc9.nomfs", true); if (nowidelut) run("abc9 -maxlut 4 -W 200"); else diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 1c190d37e..eb9fa1e82 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -613,6 +613,8 @@ struct SynthXilinxPass : public ScriptPass if (family != "xc7") log_warning("'synth_xilinx -abc9' not currently supported for the '%s' family, " "will use timing for 'xc7' instead.\n", family.c_str()); + if (!help_mode && !active_design->scratchpad.count("abc9.nomfs")) + active_design->scratchpad_set_bool("abc9.nomfs", true); std::string techmap_args = "-map +/xilinx/abc9_map.v -max_iter 1"; if (dff_mode) techmap_args += " -D DFF_MODE"; |