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authorgatecat <gatecat@ds0.me>2022-11-16 13:35:37 +0100
committermyrtle <gatecat@ds0.me>2022-11-17 13:34:58 +0100
commitb6467f080102834c82718470d706c4a848a6cb90 (patch)
tree881c57508f3ae2964ec4f99100cbbd91fd06da61 /techlibs
parentf111bbdf4006be9f108374c8591c682f02033a6f (diff)
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fabulous: Allow adding extra custom prims and map rules
Signed-off-by: gatecat <gatecat@ds0.me>
Diffstat (limited to 'techlibs')
-rw-r--r--techlibs/fabulous/synth_fabulous.cc32
1 files changed, 32 insertions, 0 deletions
diff --git a/techlibs/fabulous/synth_fabulous.cc b/techlibs/fabulous/synth_fabulous.cc
index 11c415c03..d7c45e094 100644
--- a/techlibs/fabulous/synth_fabulous.cc
+++ b/techlibs/fabulous/synth_fabulous.cc
@@ -65,6 +65,14 @@ struct SynthPass : public ScriptPass
log(" -plib <primitive_library.v>\n");
log(" use the specified Verilog file as a primitive library.\n");
log("\n");
+ log(" -extra-plib <primitive_library.v>\n");
+ log(" use the specified Verilog file for extra primitives (can be specified multiple\n");
+ log(" times).\n");
+ log("\n");
+ log(" -extra-map <techamp.v>\n");
+ log(" use the specified Verilog file for extra techmap rules (can be specified multiple\n");
+ log(" times).\n");
+ log("\n");
log(" -encfile <file>\n");
log(" passed to 'fsm_recode' via 'fsm'\n");
log("\n");
@@ -112,6 +120,8 @@ struct SynthPass : public ScriptPass
}
string top_module, json_file, blif_file, plib, fsm_opts, memory_opts;
+ std::vector<string> extra_plib, extra_map;
+
bool autotop, forvpr, noalumacc, nofsm, noshare, noregfile, iopad, complexdff, flatten;
int lut;
@@ -179,6 +189,14 @@ struct SynthPass : public ScriptPass
plib = args[++argidx];
continue;
}
+ if (args[argidx] == "-extra-plib" && argidx+1 < args.size()) {
+ extra_plib.push_back(args[++argidx]);
+ continue;
+ }
+ if (args[argidx] == "-extra-map" && argidx+1 < args.size()) {
+ extra_map.push_back(args[++argidx]);
+ continue;
+ }
if (args[argidx] == "-nofsm") {
nofsm = true;
continue;
@@ -237,6 +255,12 @@ struct SynthPass : public ScriptPass
else
run("read_verilog -lib " + plib);
+ if (help_mode) {
+ run("read_verilog -lib <extra_plib.v>", "(for each -extra-plib)");
+ } else for (auto lib : extra_plib) {
+ run("read_verilog -lib " + lib);
+ }
+
if (check_label("begin")) {
if (top_module.empty()) {
if (autotop)
@@ -325,6 +349,14 @@ struct SynthPass : public ScriptPass
}
run("techmap -map +/fabulous/latches_map.v");
run("techmap -map +/fabulous/ff_map.v");
+ if (help_mode) {
+ run("techmap -map <extra_map.v>...", "(for each -extra-map)");
+ } else if (!extra_map.empty()) {
+ std::string map_str = "techmap";
+ for (auto map : extra_map)
+ map_str += stringf(" -map %s", map.c_str());
+ run(map_str);
+ }
run("clean");
}